1. Field of the Invention
The present invention relates to methods and apparatus for implementing a standby mode in a random access memory and, more particularly, to techniques for controlling the standby mode in the generator system of a random access memory using an existing self-refresh oscillator to ensure the generator system experiences sufficiently long active states to maintain internal functions.
2. Description of the Related Art
In electronic memory devices, such as dynamic random access memories (DRAMs), it is often desirable to conserve power. For example, conventional DRAM chips are capable of entering a power down state or a standby state when commanded by an external signal or via on-chip control signals. During a standby state, the chip conserves power by temporarily reducing the amount of power consumed by certain components on the chip. To ensure proper chip operation, the chip maintains necessary circuits in an active state, such as the receivers, which are responsible for receiving external signals, and the self-refresh block, which is responsible for periodically refreshing the charge levels in the memory array. Other circuits, such as the generator system, may have their power reduced or removed during standby mode.
The generator system of a DRAM chip is essentially the portion of chip responsible for receiving an external power supply (VDD) and generating all internal voltages and currents required by the chip to operate. The internal voltages include internal supply voltages, which are typically applied to some type of load within the chip (e.g., the memory array), and internal reference voltages, which are used by on-chip comparators to determine whether certain voltage levels on the chip are above or below pre-determined target levels. The generator system may supply internal currents for the refresh clock, charging capacitances, etc. Typically, the generator system includes a number of individual generators respectively associated with specific supply voltages, reference voltages, or supply currents. More specifically, the generator system includes a voltage reference system as well as active generators such as voltage pumps and voltage regulators.
In a fully active state, a DRAM generator system consumes significant power. Consequently, it is desirable to switch the generator system to a lower power state or standby mode when possible. Some generators, for example, use a differential amplifier with less bias current or a resistor divider with higher resistors, thereby requiring less current. Other generators operate at half power compared to active operation thus facilitating lower current consumption.
If a DRAM chip is in a standby mode when an external command, such as a read or write command, is received, the chip must immediately transition to an active mode to respond to the command. External commands detected by the chip's receiver are supplied to a command decoder that translates external commands into corresponding internal command signals. A global controller responds to the internal command signals by generating a corresponding set of output signals, which are routed to the various portions of the DRAM chip to carry out the requested operation. In particular, the global controller generates an internal signal (BNKIDLE) that indicates to the generator system whether the chip is in an active or standby state (e.g., BNKIDLE high=standby state; BNKIDLE low=active state). Upon receipt of an external command, the global controller immediately sets the BNKIDLE signal to the active state, thereby causing the generator system to supply all necessary voltages and currents to the DRAM chip.
Even in a standby state, the generator systems of typical commodity DRAMs still consume considerable current, for example, by continuously supplying reference voltages to comparators to determine if operational voltages are at target levels. For low-power, specialized DRAMs such as those used in mobile applications (e.g., cellular RAMs), the specifications for current usage in standby mode are even more stringent than in commodity DRAMs. To meet the standby requirements of such devices, a clocked standby mode can be employed. In a clocked standby mode, when the DRAM chip experiences an extended standby state, the generator system periodically alternates between an active or “enabled” standby state and an off or “disabled” standby state, such that the generator system is activated only for short periods of time while the chip is in a standby state, e.g., less than 10% of the time. During a continuous period of time in which no external command is received, the generator may periodically enter the enabled standby state for an operational period of time (toper) followed by a disabled standby state for a disabled period of time (tdisable) (this periodic cycle is interrupted when an external command is received). For example, operational time toper may be a few microseconds long and constitute roughly a tenth of the overall cycle time (tcycle=toper+tdisable) of the clocked standby mode. During the disabled standby state of the clocked standby mode, the whole generator system is disabled with the exception of a few circuits, such as VDD and PWRON-detection. Thus, the generator system is inactive about 90% of the time, facilitating markedly reduced power consumption in a clocked standby state as compared to conventional approaches.
Within the periodic enabled standby state, the activated generator system is able to restore voltage and current levels to compensate for any voltage drops that may have resulted from leakage or refresh operations during the disabled period. Reference voltage generators typically require a few microseconds to establish a stable, target voltage level. The active state of the clocked standby state can be correlated to the refresh related loads required by the memory device so that any voltage ripple will be well controlled.
The internal signal, BNKIDLE, can be used to facilitate the functioning of the above-described clocked standby mode. For example, every rising edge of the BNKIDLE signal can be used to set the generator system in the disabled phase of the clocked standby mode for the period tdisable. With every falling edge of BNKIDLE, the generator system enters the briefer enabled period toper.
Depending upon the system configuration, external commands sent to a DRAM chip can be very brief pulses. If purely following an external command, the BNKIDLE signal can be low (indicating an active state) less than 20 nanoseconds (ns). The generator system is typically designed to react quickly to transitions of BNKIDLE from a standby state to an active state (e.g., transitions from a high to low state) to rapidly begin supplying and establishing necessary voltages and currents at defined, stable levels. Nevertheless, such short active state durations may not be sufficient to permit certain generators to fully respond to the active state. For example, generators responsible for establishing reference voltages typically require significantly longer active periods to supply an accurate, stable voltage to a comparator (e.g., on the order of a few microseconds). To compensate, certain individual generators within the generator system may internally delay the transition back to standby mode to provide additional time to react to an active state command. Even these measures, however, may be insufficient to assure that the active generators are able to react to any voltage drop (or current draw) occurring during a very short (pulsed) active state period or during a subsequent standby state, particularly when large variations in duration of the states occur.
One solution to address brief active states is to individually delay the rising edge of BNKIDLE within certain generators of the generator system, for example, by durations between 80 and 500 ns. This approach, which has been implemented with active generators such as voltage regulators and voltage pumps, does not cause a delay centrally within the generator block but individually for the active generators. With such local delays, a minimum active phase of each active generator is set independent of the pattern of the BNKIDLE signal. In this manner, un-stabilized voltages within resistor divider and differential amplifier circuits can generally be avoided. Signal patterns with short BNKIDLE low phases can be handled, because a minimum active time of the active generators such as voltage regulators and voltage pumps guarantees that the charge will be recovered on the decoupling capacitances at the internal voltages.
Generators in the generator system responsible for producing reference voltages typically have been treated differently. Generally, the reference voltage system is always active and therefore independent of BNKIDLE. In some cases, the reference voltage system always remains active but is capable of switching between different power supply currents depending upon the state of BNKIDLE. Nevertheless, a memory device employing all generators together will experience a variety of slightly different delays, such that a phase exists where one generator is still in an active state while another generator is in a standby state.
From a system overview standpoint, the foregoing approach makes it is difficult to keep track of which of the generators within the generator system is delaying the rising edge of BNKIDLE and by what duration. This approach also makes the system design more complex and prone to design errors and oversights. For example, there is a risk during design of a specific circuit within the generator system that the wrong edge will be delayed (falling edge of BNKIDLE instead of the rising edge). Moreover, the delay itself may vary among the generators, due primarily to reuse reasons. Another shortcoming of designing generators with built-in delay mechanisms for delaying the transition to standby mode is that such delays are typically implemented using resistor-capacitor (RC) circuits, which take up considerable space on the chip.
Further, the solution of delaying the rising edge of BNKIDLE for 80 to 500 ns in certain active generators may not prevent failure of the generator system of a DRAM chip under certain signal patterns and, in particular, a generator system using the clocked standby mode may be particularly susceptible to losing margin and failing under certain signal patterns. Specifically, a series of very brief (e.g., tens of nanoseconds) active states spaced apart by standby periods on the order of hundreds of nanoseconds may cause reference voltage levels (which may require several microseconds to stabilize) to gradually degrade from target levels.